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Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE
The Advance Formal Verification team is dedicated to formal verification. It provides formal functional and security verification for a broad range of IPs including input-output virtualization, PCIe Root-Complex/End-Point, inter-chiplet highspeed connections, etc. We are currently looking for formal verification engineers with expertise in IP verification, formal verification techniques, highspeed IO bus protocols and team leadership to take on the challenges. In these highly visible roles, the qualified candidates will use cutting edge formal verification technologies to verify the newest IPs resulting in a level of design quality not paralleled by classical verification.
KEY RESPONSIBILITIES
- Collaborating with architects and designers to understand the design intents
- Creating and executing formal verification plans for design blocks
- Writing and debugging properties to verify the design, analyzing counter-examples and pushing for the resolution
- Optimizing runtime using formal techniques
- Collecting and reporting status and progress
- Improving formal setups based on feedbacks from reviews, metrics, etc
- Leading and coordinating verification activities for a small team
- Training and couching junior engineers
- Developing working procedures, flows and infra
- Handling complicated formal problems
- Developing AI skill to assistant formal verification, and leverage AI to make FV can be widely used in multiple IP blocks and IP team members for different purpose.
PREFERRED EXPERIENCE
- Design or verification experience in ASIC or FPGA
- Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods
- Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.)
- Extensive experience verifying complex, packet or control based designs
- Familiarity with industry standard high-speed protocols such as PCIe, AXI, etc
- Experience with verification of Hardware-Firmware interaction
- AI capability is a plus:
- Experience leveraging AI-assisted tools to improve formal verification productivity, including property development, proof analysis, coverage assessment, and debug.
- Ability to apply Generative AI technologies to automate engineering workflows, accelerate root-cause analysis, and improve verification efficiency.
- Experience creating, customizing, or optimizing AI prompts, skills, agents, or workflows to support engineering tasks and team productivity.
ACADEMIC CREDENTIALS
- BS (or higher) degree in Electronics/Electrical or Computer Engineering desired
LOCATION: Shanghai, Beijing
- #LI-JW3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.